1. Field of the Invention
This invention relates generally to semiconductor processing, and, more particularly, to selecting wafers for sampling during semiconductor processing.
2. Description of the Related Art
A semiconductor fabrication facility typically includes numerous processing tools used to fabricate semiconductor devices. The processing tools may include photolithography steppers, etch tools, deposition tools, polishing tools, rapid thermal processing tools, ion implantation tools, and the like. Wafers (or wafer lots) are processed in the tools in a predetermined order and each processing tool modifies the wafers according to a particular operating recipe so that a desired product is formed in or on the wafer. For example, a photolithography stepper may be used to form a patterned layer of photoresist above the wafer. Features in the patterned layer of photoresist correspond to a plurality of features, e.g. gate electrode structures, which will ultimately be formed above the surface of the wafer. When processing of the wafer is complete, the various features formed in or on the wafer, as well as features formed in or on layers that are deposited above the wafer, combine to form the desired product. Exemplary products include processors, memory elements, and the like.
The semiconductor fabrication facility typically also includes metrology tools for collecting data indicative of the physical state of one or more wafers before, during, and/or after processing by the processing tools. Collecting the data indicative of the physical state of a wafer using a metrology tool is conventionally referred to as “sampling” the wafer. Data collected by the metrology tools may be used to characterize the wafer, to detect faults associated with the processing, and/or to determine (or predict) the quality of the finished product. For example, a mean critical dimension associated with the various features, e.g. gate electrode structures, may be indicative of a performance level of products formed on the wafer and/or the wafer lot. If the wafer state data indicates that the mean critical dimension associated with the feature, e.g. a gate electrode, is on the lower end of an allowable range for such feature sizes, then this may indicate that the product formed on the wafer may exhibit relatively high performance levels. For example, smaller feature sizes in a processor formed on the wafer may be associated with faster processing speeds. Higher performance products may be sold at a higher price, thereby increasing the profitability of the manufacturing operation.
High-volume semiconductor fabrication facilities may process hundreds or even thousands of wafer lots every week. Sampling every processed wafer (or wafer lot) may significantly reduce the efficiency of the semiconductor fabrication facility, at least in part because metrology generally takes longer than processing. Accordingly, only a portion of the wafers processed in the facility are typically sampled. For example, a wafer lot including 25 wafers may be processed using a three-chambered etching tool. To monitor the operation of each chamber of the etching tool, an engineer may select particular slots in a run to be sampled by a metrology tool and include these selections in a sampling plan. If the wafers are provided to the chambers of the etching tool sequentially, one possible sampling plan could be to perform metrology on the first wafer, which should be provided to the first chamber, on the 11th wafer, which should be provided to the second chamber, and on the 24th wafer, which should be provided to the third chamber.
Static sampling plans, such as the one described above, are appropriate as long as the manufacturing environment in the semiconductor fabrication facility is also static. However, the manufacturing environment is typically not static and changes in the manufacturing environment may cause metrology tools operating according to the static sampling plan to sample a less desirable subset of the wafers. For example, the metrology tool cannot sample the 24th wafer, as indicated by the static sampling plan, if the number of wafers in the lot changes from 25 to 20. Consequently, wafers processed by the third chamber of the etching tool will not be sampled and engineers will have no indication of whether or not the third chamber of the etching tool is operating correctly. Engineers may be able to change the sampling plan manually, but manual intervention is time-consuming, labor-intensive, and may reduce the efficiency of the semiconductor fabrication facility. Furthermore, engineers may not be aware of the changes in the manufacturing environment until many wafers and/or wafer lots have been processed using the incorrect, undesirable, or non-optimal static sampling plan.